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Intel 8237 is a direct memory access (DMA) controller

  • Intel 8237 is an immediate memory get to (DMA) controller, a part of the MCS 85 microchip family. It empowers information exchange amongst memory and the I/O with lessened load on the framework's primary processor by giving the memory control signs and memory address data amid the DMA exchange. 

  • The 8237 is a four-channel gadget that can be extended to incorporate any number of DMA channel inputs. The 8237 is equipped for DMA exchanges at rates of up to 1.6 MByte every second. Every channel is equipped for tending to an entire 64k-byte segment of memory and can exchange up to 64k bytes with a solitary programming.[1] 

  • A solitary 8237 was utilized as the DMA controller as a part of the first IBM PC and IBM XT. The IBM PC AT included another 8237 in ace slave setup, expanding the quantity of DMA channels from four to seven.[2] Later IBM-good PCs may have chip sets that imitate the elements of the 8237 for in reverse compatibility.The 8237 works in four unique modes, contingent on the quantity of bytes exchanged per cycle and number of ICs utilized: 

  • Single - One DMA cycle, one CPU cycle interleaved until address counter achieves zero.[3] 

  • Piece - Exchange advances until the word number achieves zero or the EOP flag goes active.[3] 

  • Request - Exchanges proceed until TC or EOP goes dynamic or DRQ goes dormant. The CPU is allowed to utilize the transport when no exchange is requested.[3] 

  • Course - Used to course extra DMA controllers. DREQ and DACK is coordinated with HRQ and HLDA from the following chip to set up a need chain. Real transport signs is executed by fell chip.[3] 

  • Memory-to-memory exchange can be performed. This implies information can be exchanged starting with one memory gadget then onto the next memory gadget. The channel 0 Current Address enroll is the hotspot for the information exchange and channel 1 and the exchange ends when Current Word Check enlist gets to be 0. Channel 0 is utilized for Measure revive on IBM PC compatibles.[3] 

  • In auto introduce mode the address and number qualities are endless supply of an end of process (EOP) flag. This happens with no CPU mediation. It is utilized to rehash the last transfer.[3] 

  • The terminal check (TC) signals end of exchange to ISA cards. Toward the end of exchange an auto introduce will happen designed to do as such. 

  • Single mode[edit] 

  • In single mode one and only byte is exchanged per ask. For each exchange, the checking register is decremented and address is augmented or decremented relying upon programming. At the point when the tallying register achieves zero, the terminal number TC flag is sent to the card.[4][5] 

  • The DMA ask for DREQ must be raised by the card and held dynamic until it is recognized by the DMA recognize DACK.[4] 

  • Square exchange mode[edit] 

  • The exchange is initiated by the DREQ which can be deactivated once recognized by DACK. The exchange proceeds until end of process EOP (either inward or outside) is enacted which will trigger terminal tally TC to the card. Auto-instatement might be customized in this mode.[4] 

  • Request exchange mode[edit] 

  • The exchange is initiated by DREQ and recognized by DACK and proceeds until either TC, outer EOP or DREQ goes dormant. Just TC or outside EOP may actuate auto-instatement if this is programmed.[4] 

  • Inside registers[edit] 

  • The inside registers utilized as a part of the 8237 for information exchange are as per the following: 

  • Base address enlist: To store the underlying location from where information exchange will happen 

  • Base word check enlist: To store the quantity of exchanges to be performed 

  • Current address enlist: To store the present address from where information is being exchanged 

  • Current word tally enlist: To store the quantity of exchanges staying to be performed 

  • Impermanent address enroll: To hold address of information amid memory-to-memory exchange 

  • Brief word check enroll: To hold number of exchanges to be performed in memory-to-memory exchange 

  • Mode enroll: 8-bit enlist which stores the channel to be utilized, the working mode, i.e. the exchange mode, and other exchange parameters 

  • Summon enlist: 8-bit enroll which introduces the channel to be utilized for information exchange 

  • Ask for enlist: 8-bit enroll used to show which channel is asking for information exchange 

  • Cover enroll: 8-bit enlist used to veil a specific channel from asking for DMA benefit 

  • Status enroll: 8-bit enlist used to demonstrate which channel is as of now under DMA administration and some different parametersAs an individual from the Intel MCS-85 gadget family, the 8237 is a 8-bit gadget with 16-bit tending to. Be that as it may, it is perfect with the 8086/88 chip. The IBM PC and PC XT models (machine sorts 5150 and 5160) have a 8088 CPU and a 8-bit framework transport engineering; the last interfaces straightforwardly to the 8237, yet the 8088 has a 20-bit address transport, so four extra 4-bit address locks, one for each DMA channel, are added close by the 8237 to expand the address counters. Notwithstanding, in light of the fact that these outside hooks are separate from the 8237 address counters, they are never consequently augmented or decremented amid DMA operations, making it difficult to play out a DMA operation over a 64 KiB address limit. Endeavors to cross a 64 KiB limit in a DMA exchange will wrap around inside one 64 KiB square of memory. (For instance, if a DMA channel and the related deliver hook were modified to exchange 256 bytes to rising locations beginning at address 0x3FF8C, rather than exchanging to addresses 0x3FF8C through 0x4008B, information would be exchanged to addresses 0x3FF8C through 0x3FFFF and after that to 0x30000 through 0x3008B.) 

  • The IBM PC AT (machine sort 5170) and 100% compatibles utilize a 80286 CPU and a 16-bit framework transport engineering. Notwithstanding the 8237 from the PC and XT models, a second, fell 8237 is included, for 16-bit DMA exchanges. This is conceivable, in spite of the 8237 being a 8-bit gadget, on the grounds that the 8237 performs exchanges between an I/O port and memory as "fly-by" moves in which the information is put onto the transport by the source memory or I/O port and specifically read in the meantime by the goal I/O port or memory, without being taken care of by the 8237. For this method of exchange, the width of the information transport is basically insignificant to the 8237 (the length of it is associated with an information transport no less than 8 bits wide, to programme the 8237 registers). The second 8237 in an AT-class PC gives three 16-bit DMA channels (its channels 1 through 3, named diverts 5 through 7 in the PC AT); its channel 0 (named direct 4 in the PC AT) is utilized as a part of course mode to associate the 8237 for 8-bit DMA as the "slave" in the course plan; the 8237 giving the 16-bit channels is the "ace". With the goal that it can address 16-bit words, it is associated with the address transport in a manner that it numbers even addresses (0, 2, 4, ...) rather than single locations. Like the initial 8237, it is increased with four address-augmentation registers. In an AT-class PC, every one of the eight of the address growth registers are 8 bits wide, so that full 24-bit addresses—the extent of the 80286 address transport—can be determined. DMA exchanges on any channel still can't cross a 64 KiB limit. (16-bit DMA is constrained to 32,768 16-bit words, despite the fact that a DMA channel can tally through 65536 locations; the most-huge piece of the address counter from a 16-bit DMA channel is disregarded.) On the grounds that the 8237 memory-to-memory DMA mode works by exchanging a byte from the source memory area to an interior transitory 8-bit enroll in the 8237 and after that from the impermanent enlist to the goal memory area, this mode couldn't be utilized for 16-bit memory-to-memory DMA, as the brief enlist is not sufficiently huge. Also, memory-to-memory 16-bit DMA would require utilization of channel 4, clashing with its utilization to course the 8237 that handles the 8-bit DMA channels. In any case, on the AT, 8-bit DMA channel 0 is no longer utilized for Measure revive, having been supplanted by particular invigorate rationale, so it ought to be conceivable to perform 8-bit memory-to-memory DMA utilizing channels 0 and 1 without interfering with Measure revive. 

  • The plan of 8237-based DMA in PC AT compatibles was not overhauled with the move to the 32-bit CPUs and 32-bit framework transport models. Thus, a restriction on these machines is that the 8237 DMA controllers with their sidekick address "page" augmentation enlists just can address 16 MiB of memory, as indicated by the first plan situated around the 80286 CPU, which itself has this same tending to limitation.[6] This implies for other memory ranges, the information must be exchanged first by DMA from the I/O gadget to a middle of the road support in the initial 16 MiB of the physical address space, and after that moved to the last memory by the CPU; or, in the other heading, it must be exchanged from the underlying memory to the halfway cradle by the CPU before being exchanged by DMA from that cushion to the I/O gadget. This system is called "ricochet cushion". As a rule, it loses any general speed advantage connected with DMA, yet it might be important if a fringe requires to be gotten to by DMA because of either requesting timing necessities or equipment interface firmness. 

  • In the PS/2 arrangement of PCs, IBM updated the DMA equipment to bolster 32-bit information and addresses in a few frameworks with 80386 CPUs, yet they did this by supplanting the 8237 with another DMA controller plan. The new plan incorporates a 8237 similarity mode for descending similarity with the PC AT. 

  • Incorporation into chipsets[edit] 

  • In spite of the fact that this gadget may not show up as a discrete part in cutting edge PC frameworks, it appears inside framework controller chip sets. For instance, the 82875P ISP incorporated framework fringe controller has two DMA interior controllers modified precisely like the 8237.

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